The present invention relates to a digital switching amplifier capable of amplifying 1-bit conversion signal, with high efficiency, that is obtained by converting an analog signal or a multi-bit signal in accordance with the delta sigma modulation.
A 1-bit signal is obtained by the delta sigma modulation is not limited to be used for recording an audio signal and transmitting among the electronic devices. It is also possible to obtain a demodulated analog signal that has been subjected to the power amplification, only by (a) sending the 1-bit signal, as it is, to a semiconductor power amplifier device so as to obtain switching pulses having a great amplitude of voltage and (b) filtering the switching pulses through a low pass filter.
Further, in the semiconductor power amplifier device a nonlinear region (a saturated region) is used for its operations, unlike the conventional amplifier in which a linear region (an unsaturated region) is used for its operations. Accordingly, the switching amplifier adopting the foregoing delta sigma modulation has the advantage that the power amplification can be made with extremely high efficiency. Because of this, the product adopting the switching amplifier has been commercialized.
The following description deals with one example of a structure of a conventional digital switching amplifier adopting the delta sigma modulation with reference to FIG. 5.
A conventional digital switching amplifier 10, as shown in FIG. 5, is mainly provided with adders 5P and 5M, a delta sigma modulation circuit 1, a constant voltage switching circuit 2, a low pass filter (LPF) network circuit 3, and an attenuation and adjustment section 9.
Differential input signals are inputted via input terminals 4P and 4M to the digital switching amplifier 10. The differential input signals are made of a pair of an analog acoustic signal S1P having a positive polarity and an analog acoustic signal S1M having a negative polarity. The delta sigma modulation circuit 1 converts the analog acoustic signals S1P and S1P into 1-bit signals S2P and S2M, respectively. Then, the 1-bit signals S2P and S2M are sent to the constant voltage switching circuit 2 in which constant voltages (+V and xe2x88x92V) are switched and amplified in accordance with the 1-bit signals S2P and S2M so as to be demodulated to analog acoustic signals by the low pass filter network circuit 3 and to be outputted via output terminals 8P and 8M, respectively. Note that the analog acoustic signal S1M having a negative polarity is obtained by reversing the polarity of the analog acoustic signal S1P having a positive polarity.
Inputted to the attenuation and adjustment section 9 are output signals S3P and S3M, of the constant voltage switching circuit 2, that are obtained by the procedure in which the 1-bit signals have been subjected to the power amplification. Inputted to the adders 5P and 5M are the analog acoustic signals S1P and S1M that have been inputted via the input terminals 4P and 4M, respectively, as well as negative feedback signals S4P and S4M from the constant voltage switching circuit 2. The adders 5P and 5M carry out the addition of the signals thus received. Output signals of the adders 5P and 5M are sent to the delta sigma modulation circuit 1.
The negative feedback signals S4P and S4M are subtracted from the analog acoustic signals S1P and S1M, respectively, and the result thus subtracted are subjected to the delta sigma modulation by the delta sigma modulation circuit 1 so as to generate the 1-bit signals S2P and S2M and output them to the constant voltage switching circuit 2, respectively.
The delta sigma modulation circuit 1 is provided with an integrator and adder group 11 and a quantization circuit 12. The integrator and adder group 11 includes high-order integrators, and the respective subtracted results are integrated and added. The results thus added are sent to the quantization circuit 12, respectively. The quantization circuit 12 judges the polarity of the output signals of the integrator and adder group 11, and converts the results thus judged into 1-bit signals S2P and S2M, respectively. Note that the quantization threshold of the quantization circuit 12 is set so as to be optimal to a sampling frequency that is to be assumed.
The quantization circuit 12 operates in accordance with a clock signal (not shown). Connected with the constant voltage switching circuit 2 are (a) a constant voltage power source 6H that outputs a D.C. constant voltage +V having a positive polarity and (b) a constant voltage power source 6L that outputs a D.C. constant voltage xe2x88x92V having a negative polarity whose amplitude is same as that of the D.C. voltage +V. In the constant voltage switching circuit 2, the constant voltages +V and xe2x88x92V, which are supplied by the respective constant voltage power sources 6H and 6L, are switched in accordance with the 1-bit signals S2P and S2M, respectively.
Namely, the constant voltage switching circuit 2 amplifies the 1-bit signals S2P and S2M by using these signals as switching control signals. The constant voltage switching circuit 2 amplifies the 1-bit signals S2P and S2M and outputs the amplified results to the low pass filter network circuit 3 and the attenuation and adjustment section 9. The attenuation and adjustment section 9 is provided for attenuating and adjusting the 1-bit signals S3P and S3M that have been subjected to the power amplification and for returning to the delta sigma modulation circuit 1 by the negative feedback.
The low pass filter network circuit 3 limits to the band width of the lower frequency band so as to demodulate the 1-bit signals S3P and S3M to the analog acoustic signals, respectively. Further, the low pass filter network circuit 3 outputs the analog acoustic signals via the output terminals 8P and 8M, respectively.
The following description deals with the operation of the digital switching amplifier 10. From the analog acoustic signals S1P and S1M inputted via the input terminals 4P and 4M the negative feedback signals S4P and S4M are subtracted by the respective adders 5P and 5M, and then the subtracted results ((S1Pxe2x88x92S4P) and (S1Mxe2x88x92S4M)) are sent to the delta sigma modulation circuit 1 so as to be subjected to the delta sigma modulation and be converted into the 1-bit signals S2P and S2M. In the delta sigma modulation circuit 1, the output signals of the adders 5P and 5M are integrated by the integrator and adder group 11 and are added so as to be noise-shaped and be outputted to the quantization circuit 12 which judges the polarity of the added differential integration signals to be converted into binary 1-bit signals S2P and S2M.
The 1-bit signals S2P and S2M are sent to the constant voltage switching circuit 2 as the switching control signal, respectively, and are subjected to the power amplification so as to be signals having a voltage range between the constant voltages +V and xe2x88x92V that have been supplied from the constant voltage power sources 6H and 6L, respectively. The 1-bit signals S3P and S3M that have been subjected to the power amplification by the constant voltage switching circuit 2 are sent to the low pass filter network circuit 3 so as to be demodulated to the analog acoustic signals and to be outputted outside via the output terminals 8P and 8M, respectively. The 1-bit signals S3P and S3M that have been subjected to the power amplification are returned by the negative feedback to the delta sigma modulation circuit 1 via the attenuation and adjustment section 9 and the respective adders 5P and 5M.
By the way, according to the foregoing conventional digital switching amplifier 10, the analog acoustic signal outputted via the output terminals 8P and 8M includes a voltage difference (i.e., an offset voltage) between the D.C. components of the respective output terminals 8P (positive output terminal) and 8M (negative output terminal) due to various reasons. This causes the occurrence of a noise in the lower frequency band. This also causes speakers (not shown) to generate a pop in response to the power ON and OFF when the speakers are connected with the output terminals 8P and 8M.
The following are main reason why such an offset voltage occurs: (a) such an offset voltage occurs from operational amplifiers (not shown) in the delta sigma modulation circuit 1; (b) the absolute values of the respective constant voltages +V and xe2x88x92V that have been sent from the constant voltage power sources 6H and 6L to the constant voltage switching circuit 2 are not coincident with each other (uneven); (c) a level difference occurs between the positive and negative signals of the differential negative feedback signal (i.e., a D.C. voltage level difference between the negative feedback signals S4P and S4M); and (d) the voltage characteristics are not coincident with each other due to the unevenness of wiring patterns of the circuit voltage characteristics.
The foregoing conventional digital switching amplifier 10 cancels the offset voltage as follows. More specifically, the constant voltages +V and xe2x88x92V of the respective constant voltage power sources 6H and 6L that are sent to the constant voltage switching circuit 2 are adjusted, thereby canceling the offset voltage in the output signals. Alternatively, the attenuation factors are adjusted, when the output signals S3P and S3M of the constant voltage switching circuit 2 are attenuated so as to return to the delta sigma modulation circuit 1 by the negative feedback, thereby canceling the offset voltage in the output signals.
The following description deals with how the offset voltage is adjusted in the digital switching amplifier 10.
In the digital switching amplifier 10, the 1-bit signals S3P and S3M that have been subjected to the power amplification are attenuated by respective variable attenuators 9P and 9M in the attenuation and adjustment section 9 so as to output the negative feedback signals S4P and S4M to the delta sigma modulation circuit 1. However, in ordinary, the output signals of the amplifier include an offset voltage due to the offset voltage in the delta sigma modulation circuit 1, the unevenness of the absolute values of the constant voltages +V and xe2x88x92V of the respective constant voltage power sources 6H and 6L that are sent to the constant voltage switching circuit 2, or other reasons.
An offset voltage occurs due to the following reasons other than the foregoing reasons. More specifically, when the attenuation factors are not coincident with each other between the respective variable attenuators 9P and 9M in the attenuation and adjustment section 9, a D.C. voltage level difference occurs between the negative feedback signals S4P and S4M that are the output signals of the respective variable attenuators 9P and 9M even when the D.C. voltage levels of the 1-bit signals S3P and S3M that are the output signals of the constant voltage switching circuit 2 are coincident with each other. This causes such an offset voltage.
Accordingly, when an offset occurs, the digital switching amplifier 10 intentionally makes the voltage level of the negative feedback signal S4P different from the negative feedback signal S4M, thereby enabling to cancel the offset voltage.
However, according to the foregoing offset voltage adjustment, since the D.C. voltage levels of the negative feedback signals S4P and S4M are respectively adjusted by changing the attenuation factors of the respective variable attenuators 9P and 9M, the following problem arises.
More specifically, since the absolute values of the voltage levels of the negative feedback signals S4P and S4M respectively change, the gain of the conventional digital switching amplifier 10 changes, accordingly. In this case, it is likely that there occurs a volume difference between the light and left channels when adopting two channels of the digital switching amplifiers 10 that are connected in parallel with each other as a stereo amplifier for amplifying a stereo acoustic signal.
Further, since the D.C. voltage levels of the negative feedback signals S4P and S4M are not coincident with each other (the negative feedback signals S4P and S4M respectively change), the transfer characteristics, that the algorithm requires, are not maintained when the output signals of the adders 5P and 5M are integrated by the integrator and adder group 11 and are added so as to be noise-shaped. This causes (a) the remaining noise to increase or (b) the maximum permissible doses (oscillation limits) of the input signals (analog acoustic signals S1P and S1M) with regard to the negative feedback signals S4P and S4M respectively to change.
As has been described, the foregoing conventional art causes that the maximum output of the digital switching amplifier 10 changes and the S/N ratio becomes lowered. This causes the problem that it is not possible to obtain a target frequency band and a target dynamic range.
The present invention is made in view of the foregoing problem, and its object is to provide a digital switching amplifier which can avoid that the gain with respect to positive and negative input signals changes due to the adjustment of an offset voltage and can avoid that the noise occurs in the lower frequency band due to the offset voltage.
In order to achieve the foregoing object, a digital switching amplifier of the present invention in which a first signal and a second signal that is obtained by inverting the first signal are subjected to delta sigma modulation by a delta sigma modulation circuit so as to generate 1-bit signals, respectively, and the 1-bit signals are subjected to power amplification, the first and second signals forming a differential input signal is characterized by the following. More specifically, the digital switching amplifier includes (a) attenuation sections that attenuate the respective 1-bit signals that have been subjected to the power amplification; and (b) an offset voltage addition and adjustment section that adds adjustment voltages to output signals of the respective attenuation sections so that a D.C. voltage level difference between negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero.
With the invention, the first signal and the second signal that is obtained by inverting the first signal which constitute the differential signal are respectively subjected to the delta sigma modulation by the delta sigma modulation circuit. The first and second signals are modulated to the 1-bit signals, respectively. The respective 1-bit signals are further subjected to the power amplification. The respective 1-bit signals that have been thus subjected to the power amplification are attenuated by the attenuation sections, and thereafter are returned by the negative feedback to the delta sigma modulation circuit via the offset voltage addition and adjustment section.
By the way, in the digital switching amplifier, in ordinary, there occurs a D.C. voltage level difference between the 1-bit signals that have been subjected to the power amplification. This causes the occurrence of a noise in the lower frequency band. This also causes speakers (not shown) to generate a pop in response to the power ON and OFF when being connected to the speakers after the analog modulation.
In order to overcome the deficiency, the foregoing conventional digital switching amplifier cancels the offset voltage as follows. More specifically, the constant voltages of positive and negative polarities that are applied during the power amplification are adjusted, thereby enabling to cancel the offset voltage. Alternatively, the attenuation factors of the attenuation sections are respectively adjusted so as to intentionally make a D.C. voltage level difference between the negative feedback signals, thereby enabling to cancel the offset voltage. However, the adjustment of the attenuation factors of the respective attenuation sections causes the following new problem.
More specifically, when the attenuation factors of the attenuation sections are respectively adjusted so as to cancel the offset voltage, the absolute levels of the negative feedback signals change (not become equal to each other), thereby substantially changing the gain of the digital switching amplifier. When adopting two channels of the conventional digital switching amplifiers that are connected in parallel with each other as a stereo amplifier for amplifying a stereo acoustic signal, it is most likely that there occurs a volume difference between the light and left channels.
Further, since the transfer characteristics, that the algorithm requires, are not maintained when integration and addition are made by the delta sigma modulation circuit so as to be noise-shaped, (a) the remaining noise increases or (b) the maximum permissible doses (oscillation limits) of the differential input signals with regard to the negative feedback signals respectively change. Namely, the maximum output of the digital switching amplifier changes and the S/N ratio becomes lowered. This causes the problem that it is not possible to obtain a target frequency band and a target dynamic range.
The conventional problem is resolved by the present invention as follows. More specifically, the 1-bit signals that have been subjected to the power amplification are attenuated by the attenuation sections, respectively. Instead of the conventional case where the attenuation factors of the attenuation sections are respectively adjusted so as to intentionally make a D.C. voltage level difference between the output signals of the attenuation sections (the negative feedback signals that are returned to the delta sigma modulation circuit by the negative feedback), according to the present invention, the offset voltage addition and adjustment section adds the adjustment voltages to the output signals of the respective attenuation sections so that the D.C. voltage level difference between the negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero. This allows a return to the differential negative feedback signals whose D.C. voltage levels are coincident with each other to the delta sigma modulation circuit by the negative feedback with the addition of the adjustment voltages and without adjusting the attenuation factors of the respective attenuation sections.
Namely, even when an offset voltage occurs in the digital switching amplifier, the differential negative feedback signals whose D.C. voltage levels are coincident with each other are returned to the delta sigma modulation circuit by the negative feedback so as to adjust the offset voltage to be substantially zero, only by adding the adjustment voltages to the output signals of the respective attenuation sections via the offset voltage addition and adjustment section while measuring the offset voltage during a period such as the checking conducted just after manufacturing of the digital switching amplifier.
As described above, even when the attenuation factors are different between the attenuation sections, the D.C. voltage level difference of the negative feedback signals that are returned to the delta sigma modulation circuit becomes substantially zero (the absolute D.C. voltage levels of the differential negative feedback signals are coincident with each other). This allows to ensurely avoid that the gain of the digital switching amplifier changes and to easily avoid that the noise occurs in the lower frequency band due to the offset voltage, because the transfer characteristics, that the algorithm requires, are maintained in the digital sigma modulation circuit. Further, it is possible to prevent from occurring that (a) the remaining noise increases or (b) the maximum permissible doses (oscillation limits) of the differential input signals with regard to the negative feedback signals respectively change. Namely, it is prevented from occurring that the maximum output of the digital switching amplifier changes and the S/N ratio becomes lowered. This allows to ensurely obtain a target frequency band and a target dynamic range.
It is preferable that the offset voltage addition and adjustment section is provided between the attenuation sections and the delta sigma modulation circuit and is provided with: (a) first and second resistors, one ends of the respective first and second resistors being connected with the delta sigma modulation circuit and each of other ends being connected with the respective attenuation sections; and (b) a rheostat, provided between the one ends of the respective first and second resistors, having a movable terminal through which a predetermined analog voltage or a ground level is applied.
With the arrangement, the output signals of the respective attenuation sections are sent to the delta sigma modulation circuit via the first and second resistors. Meanwhile, the predetermined analog voltage or the ground level is applied to the rheostat via the movable terminal. This allows the resistances on both sides of the movable terminal in the rheostat to vary depending on the movement of the movable terminal of the rheostat. The adjustment voltages vary depending on the respective resistances. The adjustment voltages are added to the output signals of the respective attenuation sections and are adjusted so that the D.C. voltage level difference between the negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero. Since it is possible to make the absolute D.C. voltage levels of the differential negative feedback signals be equal to each other, it is possible (a) to ensurely avoid that the gain of the digital switching amplifier changes and (b) to easily avoid that the noise occurs in the lower frequency band due to the offset voltage.
Another digital switching amplifier of the present invention in which a first signal and a second signal that is obtained by inverting the first signal are subjected to delta sigma modulation by a delta sigma modulation circuit so as to generate 1-bit signals, respectively, and the 1-bit signals are subjected to power amplification, the first and second signals forming a differential input signal is characterized by the following. More specifically, the digital switching amplifier includes (a) an offset voltage addition and adjustment section that adds adjustment voltages to the 1-bit signals that have been subjected to the power amplification so that a D.C. voltage level difference between negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero; and (b) attenuation sections that attenuate the respective output signals of the offset voltage addition and adjustment section so as to obtain the negative feedback signals.
With the invention, the first signal and the second signal that is obtained by inverting the first signal which constitute the differential signal are respectively subjected to the delta sigma modulation by the delta sigma modulation circuit. The first and second signals are modulated to the 1-bit signals, respectively. The respective 1-bit signals are further subjected to the power amplification. The adjustment voltages are added to the respective 1-bit signals that have been thus subjected to the power amplification so that the D.C. voltage level difference between negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero. Upon receipt of the adjustment voltages, the 1-bit signals that have been subjected to the power amplification are attenuated by the attenuation sections so as to output the negative feedback signals, and thereafter the negative feedback signals are returned by the negative feedback to the delta sigma modulation circuit.
Instead of the conventional case where the attenuation factors of the attenuation sections are respectively adjusted so as to intentionally make a D.C. voltage level difference between the output signals of the attenuation sections (the negative feedback signals that are returned to the delta sigma modulation circuit by the negative feedback), according to the present invention, it is possible to return the differential negative feedback signals whose D.C. voltage levels are coincident with each other to the delta sigma modulation circuit by the negative feedback with the addition of the adjustment voltages and without adjusting the attenuation factors of the respective attenuation sections.
Namely, even when an offset voltage occurs in the digital switching amplifier, the differential negative feedback signals whose D.C. voltage level are coincident with each other are returned to the delta sigma modulation circuit by the negative feedback so as to adjust the offset voltage to be substantially zero, only by adding the adjustment voltages to the respective 1-bit signals that have been subjected to the power amplification via the offset voltage addition and adjustment section while measuring the offset voltage during a period such as the checking conducted just after manufacturing of the digital switching amplifier.
As described above, even when the attenuation factors are different between the attenuation sections, the D.C. voltage level difference of the negative feedback signals that are returned to the delta sigma modulation circuit becomes substantially zero (the absolute D.C. voltage levels of the differential negative feedback signals are coincident with each other). This allows to ensurely avoid that the gain of the digital switching amplifier changes and to easily avoid that the noise occurs in the lower frequency band due to the offset voltage, because the transfer characteristics, that the algorithm requires, are maintained in the digital sigma modulation circuit. Further, it is possible to prevent from occurring that (a) the remaining noise increases or (b) the maximum permissible doses (oscillation limits) of the differential input signals with regard to the negative feedback signals respectively change. Namely, it is prevented from occurring that the maximum output of the digital switching amplifier changes and the S/N ratio becomes lowered. This function allows a target frequency band and a target dynamic range to be obtained.
It is preferable that the offset voltage addition and adjustment section is provided with: (a) first and second resistors, one ends of the respective first and second resistors being connected with the attenuation sections, respectively, and each of other ends being connected with the respective 1-bit signals that have been subjected to the power amplification; and (b) a rheostat, provided between the one ends of the respective first and second resistors, having a movable terminal through which a predetermined analog voltage or a ground level is applied.
With the arrangement, the 1-bit signals that have been subjected to the power amplification are sent to the delta sigma modulation circuit via the first and second resistors. Meanwhile, the predetermined analog voltage or the ground level is applied to the rheostat via the movable terminal. This allows the resistances on both sides of the movable terminal in the rheostat to vary depending on the movement of the movable terminal of the rheostat. The adjustment voltages vary depending on the respective resistances. The adjustment voltages are added to the 1-bit signals that have been subjected to the power amplification and are adjusted so that the D.C. voltage level difference between the negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero. Since it is possible to make the absolute D.C. voltage levels of the differential negative feedback signals be equal to each other, it is possible (a) to ensurely avoid that the gain of the digital switching amplifier changes and (b) to easily avoid that the noise occurs in the lower frequency band due to the offset voltage.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitative of the present invention.